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T. Kenter, G. Mahale, S. Alhaddad, Y. Grynko, C. Schmitt, A. Afzal, F. Hannig, J. Förstner, and C. Plessl
OpenCL-based FPGA Design to Accelerate the Nodal Discontinuous Galerkin Method for Unstructured Meshes
In Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM). IEEE Computer Society. Apr. 2018. Accepted for publication.
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H. Riebler, G. Vaz, T. Kenter, and C. Plessl
Automated Code Acceleration Targeting Heterogeneous OpenCL Devices
In Proc. ACM SIGPLAN Symp. on Principles and practice of parallel programming (PPoPP). Pages 417–418. ACM. Feb. 2018.
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doi:10.1145/3178487.3178534
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D. Richters, M. Lass, A. Walther, C. Plessl, and T.D. Kühne
A General Algorithm to Calculate the Inverse Principal p-th Root of Symmetric Positive Definite Matrices
Communications in Computational Physics. 2018. Accepted for publication.
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arXiv:1703.02456 [math.RA]
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M. Lass, S. Mohr, H. Wiebeler, T.D. Kühne, and C. Plessl
A Massively Parallel Algorithm for the Approximate Calculation of Inverse p-th Roots of Large Sparse Matrices
In Proc. Platform for Advanced Scientific Computing (PASC). 2018. Accepted for publication.
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arXiv:1710.10899 [cs.DC]
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T. Kenter and C. Plessl
Microdisk Cavity FDTD Simulation on FPGA using OpenCL
In Proc. Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC), held in conjuction with Int. Conf. on High Performance Computing, Networking, Storage and Analysis (SC). Nov. 2016.
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M. Lass, T.D. Kühne, and C. Plessl
Using Approximate Computing in Scientific Codes
In Workshop on Approximate Computing, Embedded Systems Week. Oct. 2016.
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T. Kenter, G. Vaz, H. Riebler, and C. Plessl
Opportunities for deferring application partitioning and accelerator synthesis to runtime (extended abstract)
In Workshop on Reconfigurable Computing. Sep. 2016.
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H. Riebler, G. Vaz, C. Plessl, E.M.G. Trainiti, G.C. Durelli, E.D. Sozzo, M.D. Santambrogio, and C. Bolchini
Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems
In Proc. Int. Forum on Research and Technologies for Society and Industry (RTSI). IEEE. Sep. 2016.
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doi:10.1109/RTSI.2016.7740545
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G. Vaz, H. Riebler, T. Kenter, and C. Plessl
Potential and Methods for Embedding Dynamic Offloading Decisions into Application Code
Computers and Electrical Engineering. Jun. 2016.
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doi:10.1016/j.compeleceng.2016.04.021
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A. Agne, M. Platzner, C. Plessl, M. Happe, and E. Lübbers
ReConOS
FPGAs for Software Programmers. D. Koch, F. Hannig, and D. Ziener (eds). Springer. Switzerland. Jun. 2016. Pages 227–244.
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doi:10.1007/978-3-319-26408-0_13
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A. Lösch, T. Beisel, T. Kenter, C. Plessl, and M. Platzner
Performance-centric scheduling with task migration for a heterogeneous compute node in the data center
In Proc. Design, Automation and Test in Europe Conf. (DATE). EDA Consortium. Mar. 2016.
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A. Agne, M. Happe, A. Lösch, C. Plessl, and M. Platzner
Self-aware Computing Systems
P.R. Lewis, M. Platzner, B. Rinner, and X. Xao (eds). Springer. Switzerland. 2016. Pages 145–165.
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doi:10.1007/978-3-319-39675-0_8
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H. Riebler, G. Vaz, C. Plessl, E.M.G. Trainiti, G.C. Durelli, and C. Bolchini
Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems
In HiPEAC Workshop on Reonfigurable Computing (WRC). Jan. 2016.
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C. Plessl, M. Platzner, and P.J. Schreier
Aktuelles Schlagwort: Approximate Computing
Informatik Spektrum. (5). Oct. 2015. Pages 396–399.
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doi:10.1007/s00287-015-0911-z
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J. Torresen, C. Plessl, and X. Yao
Self-Aware and Self-Expressive Systems – Guest Editor’s Introduction
IEEE Computer. 48(7). Jul. 2015. Pages 18–20.
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doi:10.1109/MC.2015.205
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J. Schumacher et al.
Improving Packet Processing Performance in the ATLAS FELIX Project – Analysis and Optimization of a Memory-Bounded Algorithm
In Proc. Int. Conf. on Distributed Event-Based Systems (DEBS). ACM. Jun. 2015.
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M. Damschen, H. Riebler, G. Vaz, and C. Plessl
Transparent offloading of computational hotspots from binary code to Xeon Phi
In Proc. Design, Automation and Test in Europe Conf. (DATE). Pages 1078–1083. EDA Consortium. Mar. 2015.
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doi:10.7873/DATE.2015.1124
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T. Kenter, H. Schmitz, and C. Plessl
Exploring Trade-Offs between Specialized Kernels and a Reusable Overlay in a Stereo Matching Case Study
Int. Journal of Reconfigurable Computing (IJRC). 2015.
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doi:10.1155/2015/859425
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M. Damschen and C. Plessl
Easy-to-Use On-The-Fly Binary Program Acceleration on Many-Cores
In Proc. Int. Workshop on Adaptive Self-tuning Computing Systems. Jan. 2015.
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arXiv:1412.3906 [cs.DC]
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J. Anderson et al.
FELIX: a High-Throughput Network Approach for Interfacing to Front End Electronics for ATLAS Upgrades
Journal of Physics: Conference Series. 664(8). 2015. Pages 082050.
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doi:10.1088/1742-6596/664/8/082050
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T. Kenter, H. Schmitz, and C. Plessl
Kernel-centric acceleration of high accuracy stereo matching
In Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig). IEEE Computer Society. Dec. 2014.
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doi:10.1109/ReConFig.2014.7032535
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G. Vaz, H. Riebler, T. Kenter, and C. Plessl
Deferring Accelerator Offloading Decisions to Application Runtime
In Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig). IEEE Computer Society. Dec. 2014. Received best paper award.
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doi:10.1109/ReConFig.2014.7032509
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A. Agne, H. Hangmann, M. Happe, M. Platzner, and C. Plessl
Seven Recipes for Setting Your FPGA on Fire – A Cookbook on Heat Generators
Microprocessors and Microsystems. 38(8). Nov. 2014. Pages 911–919.
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doi:10.1016/j.micpro.2013.12.001
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M. Platzner and C. Plessl
Verschiebungen an der Grenze zwischen Software und Hardware
Logiken strukturbildender Prozesse: Automatismen. N.O. Eke, L. Foit, T. Kaerlein, and J. Künsemöller (eds). Wilhelm Fink. Paderborn, Germany. Oct. 2014. Pages 123–144.
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G.C. Durelli, M. Pogliani, A. Miele, C. Plessl, H. Riebler, G. Vaz, M.D. Santambrogio, and C. Bolchini
Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach
In Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA). Pages 142–149. IEEE. Aug. 2014. Invited paper.
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doi:10.1109/ISPA.2014.27
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A. Agne, M. Happe, A. Lösch, C. Plessl, and M. Platzner
Self-awareness as a Model for Designing and Operating Heterogeneous Multicores
ACM Trans. on Reconfigurable Technology and Systems (TRETS). 7(2). Jul. 2014. Pages 13:11–13:18.
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doi:10.1145/2617596
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H. Giefers, C. Plessl, and J. Förstner
Accelerating Finite Difference Time Domain Simulations with Reconfigurable Dataflow Computers
ACM SIGARCH Computer Architecture News. 41(5). Jun. 2014. Pages 65–70.
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doi:10.1145/2641361.2641372
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H. Riebler, T. Kenter, C. Plessl, and C. Sorge
Reconstructing AES Key Schedules from Decayed Memory with FPGAs
In Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM). Pages 222–229. IEEE Computer Society. Apr. 2014. Received the HiPEAC Paper Award of the HiPEAC Network of Excellence.
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doi:10.1109/FCCM.2014.67 |
Project Page
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G.C. Durelli, M. Copolla, K. Djafarian, G. Koranaros, A. Miele, M. Paolino, O. Pell, C. Plessl, M.D. Santambrogio, and C. Bolchini
SAVE: Towards efficient resource management in heterogeneous system architectures
In Proc. Int. Conf. on Reconfigurable Computing: Architectures, Tools and Applications (ARC). Springer. Apr. 2014.
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doi:10.1007/978-3-319-05960-0_38
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T. Kenter, G. Vaz, and C. Plessl
Partitioning and Vectorizing Binary Applications
In Proc. Int. Conf. on Reconfigurable Computing: Architectures, Tools and Applications (ARC). Pages 144–155. Springer. Apr. 2014.
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doi:10.1007/978-3-319-05960-0_13
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A. Agne, M. Happe, A. Keller, E. Lübbers, B. Plattner, M. Platzner, and C. Plessl
ReconOS – An Operating System Approach for Reconfigurable Computing
IEEE Micro. 34(1). Jan. 2014. Pages 60–71.
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doi:10.1109/MM.2013.110
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T. Kenter, H. Schmitz, and C. Plessl
Pragma based parallelization – Trading hardware efficiency for ease of use?
In Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig). Pages 1–8. IEEE Computer Society. Dec. 2012.
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Poster |
doi:10.1109/ReConFig.2012.6416773
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M. Happe, H. Hangmann, A. Agne, and C. Plessl
Eight Ways to put your FPGA on Fire – A Systematic Study of Heat Generators
In Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig). Pages 1–8. IEEE Computer Society. Dec. 2012. Received Best Paper Award.
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doi:10.1109/ReConFig.2012.6416745
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M. Happe, A. Agne, C. Plessl, and M. Platzner
Hardware/Software Platform for Self-Aware Compute Nodes
In Proc. Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS). Pages 8–9. Sep. 2012.
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C. Ruething, A. Agne, M. Happe, and C. Plessl
Exploration of Ring Oscillator Design Space for Temperature Measurements on FPGAs
In Proc. Int. Conf. on Field Programmable Logic and Applications (FPL). Pages 559–562. IEEE. Aug. 2012.
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doi:10.1109/FPL.2012.6339259
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B. Meyer, J. Schumacher, C. Plessl, and J. Förstner
Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort?
In Proc. Int. Conf. on Field Programmable Logic and Applications (FPL). Pages 189–196. IEEE. Aug. 2012.
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doi:10.1109/FPL.2012.6339370
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P. Barrio, T. Kenter, C. Carreras, C. Plessl, and R. Sierra
Turning control flow graphs into function calls: code generation for heterogeneous architectures
In Proc. Int. Conf. on High Performance Computing & Simulation (HPCS). Pages 559–565. IEEE. Jul. 2012.
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doi:10.1109/HPCSim.2012.6266973
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C. Plessl, M. Platzner, A. Agne, M. Happe, and E. Lübbers
Programming models for reconfigurable heterogeneous multi-cores
Awareness Magazine. Mar. 2012.
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BibTeX |
doi:10.2417/3201203.004098
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T. Schumacher, C. Plessl, and M. Platzner
IMORC: An Infrastructure and Architecture Template for Implementing High-Performance Reconfigurable FPGA Accelerators
Microprocessors and Microsystems. 36(2). Mar. 2012. Pages 110–126.
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doi:10.1016/j.micpro.2011.04.002
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M. Grad and C. Plessl
On the Feasibility and Limitations of Just-In-Time Instruction Set Extension for FPGA-based Reconfigurable Processors
Int. Journal of Reconfigurable Computing (IJRC). 2012.
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doi:10.1155/2012/418315
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T. Beisel, T. Wiersema, C. Plessl, and A. Brinkmann
Programming and Scheduling Model for Supporting Heterogeneous Accelerators in Linux
In Proc. Workshop on Computer Architecture and Operating System Co-design (CAOS). Jan. 2012.
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M. Happe, A. Agne, and C. Plessl
Measuring and Predicting Temperature Distributions on FPGAs at Run-Time
In Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig). Pages 55–60. IEEE Computer Society. Dec. 2011.
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BibTeX |
doi:10.1109/ReConFig.2011.59
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T. Kenter, C. Plessl, M. Platzner, and M. Kauschke
Estimation and Partitioning for CPU-Accelerator Architectures
In Intel European Research and Innovation Conference. Oct. 2011.
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T. Beisel, T. Wiersema, C. Plessl, and A. Brinkmann
Cooperative multitasking for heterogeneous accelerators in the Linux Completely Fair Scheduler
In Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP). Pages 223–226. IEEE Computer Society. Sep. 2011.
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Poster |
doi:10.1109/ASAP.2011.6043273
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B. Meyer, C. Plessl, and J. Förstner
Transformation of scientific algorithms to parallel computing code: subdomain support in a MPI-multi-GPU backend
In Symp. on Application Accelerators in High Performance Computing (SAAHPC). Pages 60–63. IEEE Computer Society. Jul. 2011.
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Poster |
doi:10.1109/SAAHPC.2011.12
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M. Grad and C. Plessl
Just-in-time Instruction Set Extension – Feasibility and Limitations for an FPGA-based Reconfigurable ASIP Architecture
In Proc. Reconfigurable Architectures Workshop (RAW). Pages 278–285. IEEE Computer Society. May. 2011.
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doi:10.1109/IPDPS.2011.153
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T. Kenter, M. Platzner, C. Plessl, and M. Kauschke
Performance Estimation Framework for Automated Exploration of CPU-Accelerator Architectures
In Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA). Pages 177–180. ACM. Feb. 2011.
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Poster |
doi:10.1145/1950413.1950448
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T. Schumacher, T. Süß, C. Plessl, and M. Platzner
FPGA Acceleration of Communication-bound Streaming Applications: Architecture Modeling and a 3D Image Compositing Case Study
Int. Journal of Reconfigurable Computing (IJRC). 2011.
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doi:10.1155/2011/760954
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C. Plessl and M. Platzner
Reconfigurable Embedded Control Systems: Applications for Flexibility and Agility
M. Khalgui and H.-M. Hanisch (eds). IGI Global. Hershey, PA, USA. 2011.
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doi:10.4018/978-1-60960-086-0
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A. Keller, B. Plattner, E. Lübbers, M. Platzner, and C. Plessl
Reconfigurable Nodes for Future Networks
In Proc. IEEE Globecom Workshop on Network of the Future (FutureNet). Pages 372–376. IEEE. Dec. 2010.
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BibTeX |
doi:10.1109/GLOCOMW.2010.5700341
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M. Grad and C. Plessl
Pruning the Design Space for Just-In-Time Processor Customization
In Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig). Pages 67–72. IEEE Computer Society. Dec. 2010.
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BibTeX |
doi:10.1109/ReConFig.2010.19
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C. Plessl
Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)
CSREA Press. ISBN 1-60132-140-6. Jul. 2010.
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D. Andrews and C. Plessl
Configurable Processor Architectures: History and Trends
In Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA). Pages 165. CSREA Press. Jul. 2010. Invited paper.
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T. Beisel, M. Niekamp, and C. Plessl
Using Shared Library Interposing for Transparent Acceleration in Systems with Heterogeneous Hardware Accelerators
In Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP). Pages 65–72. IEEE Computer Society. Jul. 2010.
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BibTeX |
doi:10.1109/ASAP.2010.5540798
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M. Grad and C. Plessl
An Open Source Circuit Library with Benchmarking Facilities
In Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA). Pages 144–150. CSREA Press. Jul. 2010.
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E. Lübbers, M. Platzner, C. Plessl, A. Keller, and B. Plattner
Towards Adaptive Networking for Embedded Devices based on Reconfigurable Hardware
In Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA). Pages 225–231. CSREA Press. Jul. 2010.
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M. Woehrle, C. Plessl, and L. Thiele
Rupeas: Ruby Powered Event Analysis DSL
In Proc. Int. Conf. Networked Sensing Systems (INSS). Pages 245–248. IEEE. Jun. 2010.
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doi:10.1109/INSS.2010.5572211
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T. Kenter, M. Platzner, C. Plessl, and M. Kauschke
Performance Estimation for the Exploration of CPU-Accelerator Architectures
In "Proc. Workshop on Architectural Research Prototyping (WARP)" # ", International Symposium on Computer Architecture (ISCA)". Jun. 2010.
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T. Schumacher, T. Süß, C. Plessl, and M. Platzner
Communication Performance Characterization for Reconfigurable Accelerator Design on the XD1000
In Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig). Pages 119–124. IEEE Computer Society. Dec. 2009.
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doi:10.1109/ReConFig.2009.32
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T. Schumacher, C. Plessl, and M. Platzner
An Accelerator for k-th Nearest Neighbor Thinning Based on the IMORC Infrastructure
In Proc. Int. Conf. on Field Programmable Logic and Applications (FPL). Pages 338–344. IEEE. Sep. 2009. Shortlisted for best paper award (out of 264 submissions).
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M. Grad and C. Plessl
Woolcano: An Architecture and Tool Flow for Dynamic Instruction Set Extension on Xilinx Virtex-4 FX
In Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA). Pages 319–322. CSREA Press. Jul. 2009.
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Poster
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P. Kaufmann, C. Plessl, and M. Platzner
EvoCaches: Application-specific Adaptation of Cache Mapping
In Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS). Pages 11–18. IEEE Computer Society. Jul. 2009.
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J. Beutel, S. Gruber, A. Hasler, R. Lim, A. Meier, C. Plessl, I. Talzi, L. Thiele, C. Tschudin, M. Woehrle, and M. Yuecel
Demo Abstract: Operating a Sensor Network at 3500m Above Sea Level
In Proc. Int. Conf. on Information Processing in Sensor Networks (IPSN). Pages 405–406. IEEE Computer Society. Apr. 2009.
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T. Schumacher, C. Plessl, and M. Platzner
IMORC: Application Mapping, Monitoring and Optimization for High-Performance Reconfigurable Computing
In Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM). Pages 275–278. IEEE Computer Society. Apr. 2009. Received the HiPEAC publication award.
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Poster |
doi:10.1109/FCCM.2009.25
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M. Grad and C. Plessl
Poster Abstract: Woolcano – An Architecture and Tool Flow for Dynamic Instruction Set Extension on Xilinx Virtex-4 FX
In Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM). IEEE Computer Society. Apr. 2009.
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Poster
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J. Beutel, S. Gruber, A. Hasler, R. Lim, A. Meier, C. Plessl, I. Talzi, L. Thiele, C. Tschudin, M. Woehrle, and M. Yuecel
PermaDAQ: A Scientific Instrument for Precision Sensing and Data Recovery in Environmental Extremes
In Proc. Int. Conf. on Information Processing in Sensor Networks (IPSN). Pages 265–276. IEEE Computer Society. Apr. 2009.
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M. Woehrle, C. Plessl, and L. Thiele
Rupeas: Ruby Powered Event Analysis DSL
Technical Report #290. Computer Engineering and Networks Lab. Feb. 2009.
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M. Woehrle, C. Plessl, and L. Thiele
Poster Abstract: Rupeas – An Event Analysis Language for Wireless Sensor Network Traces
In Adjunct Proc. of European Conf. on Wireless Sensor Networks (EWSN). Pages 19–20. Feb. 2009.
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Poster
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C. Plessl and M. Platzner
TKDM – A Reconfigurable Co-processor in a PC’s Memory Slot
In Proc. Int. Conf. on Field Programmable Technology (ICFPT). Pages 252–259. IEEE Computer Society. Dec. 2003.
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doi:10.1109/FPT.2003.1275755
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C. Plessl, R. Enzler, H. Walder, J. Beutel, M. Platzner, L. Thiele, and G. Tröster
The Case for Reconfigurable Hardware in Wearable Computing
Personal and Ubiquitous Computing. 7(5). Oct. 2003. Pages 299–308.
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BibTeX |
doi:10.1007/s00779-003-0243-x
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R. Enzler, C. Plessl, and M. Platzner
Virtualizing Hardware with Multi-Context Reconfigurable Arrays
In Proc. Int. Conf. on Field Programmable Logic and Applications (FPL). Pages 151–160. Springer. Sep. 2003.
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BibTeX |
doi:10.1007/b12007
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C. Plessl and M. Platzner
Instance-Specific Accelerators for Minimum Covering
Journal of Supercomputing. 26(2). Sep. 2003. Pages 109–129.
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BibTeX |
doi:10.1023/a:1024443416592
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R. Enzler, C. Plessl, and M. Platzner
Co-simulation of a Hybrid Multi-Context Architecture
In Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA). Pages 174–180. CSREA Press. Jun. 2003.
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